-------------------------------------------------------------------------------
-- File: 		shift_reg_n.vhd
-- Description:	N bits shift register. 
--				The shift is always done in the left to right direction.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity shift_reg_n is
	generic (
		N : integer
	);
	port (
		d_i     : in  std_logic_vector(N-1 downto 0);	-- Parallel in
		si_i    : in  std_logic;						-- Serial in
		l_i     : in  std_logic; 						-- Load in
		nclk_i  : in  std_logic;						-- Clock in
		so_o    : out std_logic;						-- Serial out
		q_o     : out std_logic_vector(N-1 downto 0) 	-- Parallel out
	);
end shift_reg_n;

architecture behav of shift_reg_n is
	signal r_shift : std_logic_vector(N-1 downto 0);

begin

	process(nclk_i, l_i, d_i)
	begin
		if (l_i = '1') then
			r_shift <= d_i;
		elsif (nclk_i = '0' and nclk_i'event) then
			r_shift <= si_i & r_shift(N-1 downto 1);
		end if;
	end process;

	so_o <= r_shift(0);
	q_o  <= r_shift;

end behav;
